LT8636 datasheet(13/40 Pages) AD

13 / 40 page

LT8698S/LT8698S-1

Rev. A

For more information www.analog.com

PIN FUNCTIONS

USB5V (Pin 20): USB5V is the 5V regulator feedback pin.

For cable drop compensation, the USB5V pin input cur-

rent is proportional to the sensed output current. Tie RCDC

from USB5V to the BUS/ISN output for 5V regulation plus

cable drop compensation. Tie CCDC from USB5V to BUS/

ISN to limit the cable drop compensation loop bandwidth.

Short USB5V to VBUS if no cable drop compensation is

desired.

BUS/ISN (Pin 21): BUS/ISN is the USB VBUS output and

negative current sense input pin. BUS/ISN provides an

additional input to the error amplifier to ensure the maxi-

mum output regulation voltage does not exceed 6.05V.

In addition, BUS/ISN provides the negative input to the

internal current sense amplifier. BUS/ISN must be tied

to the RSEN sense resistor for cable drop compensation

and output current limit. Kelvin connect the BUS/ISN pin

to the sense resistor to separate regulator output cur-

rent from the BUS/ISN PCB trace. See the Applications

Information section for additional operation and PCB lay-

out information.

OUT/ISP (Pin 22): OUT/ISP is the switching regulator

output. OUT/ISP must be tied to the inductor terminal

opposite the SW and must be bypassed by the output

capacitor. Also, the OUT/ISP pin is the noninverting input

to the current sense amplifier and must be tied to the

RSEN sense resistor for cable drop compensation and

output current limit. Kelvin connect the OUT/ISP pin to

the sense resistor to separate regulator output current

from the OUT/ISP trace. See the Applications Information

section for additional information.

SW (Pins 24, 25): SW is the output node of the inter-

nal top and bottom side power switches. Connect to the

switching regulator inductor. This node should be kept

small on the PCB for good performance.

BST (Pin 26): BST provides a drive voltage, higher than

the input voltage, to the top side power switch. Leave

BST floating.

PGND (Pins 27, 32): The PGND pins are the return path

of the internal bottom side power switch and must be tied

together. Place negative terminal of the input capacitors

as close as possible to the PGND pins. See Applications

Information section for a sample layout. All GND and

PGND pins are internally shorted together.

VIN (Pins 29, 30): The VIN pins are the input path of the

internal top side power switch and must be tied together.

The LT8698S requires a minimum of 2µF local input

bypass capacitance to PGND. A single 2.2µF capacitor

may be placed between VIN and PGND. Best practice for

low EMI/EMC is to tie two additional 0.1µF input bypass

capacitors to VIN. One 0.1µF capacitor should be placed

between VIN and pin 27 PGND. A second 0.1µF capacitor

of equal value should be placed between VIN and pin 32

PGND. These capacitors should be placed as close as pos-

sible to the LT8698S. See Application Information section

for a sample layout.

Exposed Pads (Pins 33–38): The exposed pads must be

connected to ground. Keep the top layer PCB connection

to these pins large to lower the thermal resistance from

the LT8698S package to ambient. See the Applications

Information section for detailed recommendations.

Corner Support Pads (Pins 39–42): The four pads at

each corner of the package are support pads intended to

improve board level mechanical reliability. These pads are

tied to ground internally to the LT8698S. The pads must

be tied to PCB ground.

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