LT8636 datasheet(12/40 Pages) AD

12 / 40 page

LT8698S/LT8698S-1

Rev. A

For more information www.analog.com

PIN FUNCTIONS

GND (Pins 1, 11, 14, 17, 23): The GND pins are the

return side of the internal control circuits and must be

tied to ground. All GND and PGND pins are internally

shorted together.

INTVCC (Pin 2): INTVCC is the bypass pin of the internal 4V

linear regulator. This pin powers the internal power switch

gate drivers and control circuits. INTVCC may be loaded

by external termination resistors up to 1mA. For reliable

operation, do not overload INTVCC. Bypass this pin to

ground with a 1µF low ESR ceramic capacitor placed close

to the LT8698S.

EN/UV (Pin 3): EN/UV is the enable and programmable

undervoltage lockout pin. The LT8698S is shut down

when the EN/UV pin is below its threshold and enabled

when above. The threshold voltage is 1.46V with EN/UV

rising and 1.31V with EN/UV falling. EN/UV below 0.25V

reduces the VIN current to <1μA. An external resistor

divider from VIN can be used to program an undervolt-

age lockout threshold below which the LT8698S will shut

down. See the Applications Information section for addi-

tional information. Tie EN/UV to VIN if not used.

FLT (Pin 4): FLT is the open drain output of the internal

fault logic. FLT pulls low after 4.2ms of a sustained fault

condition in which the output voltage is not is regulation.

FLT pulls low immediately if INTVCC < 3.6V or if the inter-

nal thermal shutdown feature activates. FLT transitions to

high impedance after 4.2ms in the sustained absence of

a fault condition. FLT is valid when VIN > 4.5V and EN/UV

> 1.46V. Float FLT if not used.

STATUS (Pin 5): STATUS is an open drain output indicator.

The STATUS pin function depends on the state selected by

the SEL1-3 pins. Refer to Table 6 for more information.

STATUS is de-bounced for 4.2ms and is valid when VIN >

4.5V and EN/UV > 1.46V. Float STATUS if not used.

SEL1, SEL2, SEL3 (Pins 6-8): SEL1-3 are tristate input

pins used to select the desired USB functionality of the

LT8698S. Refer to Table 6 in the Applications Information

section for detailed information. Tie below 0.58V for logic

low, above 1.41V for logic high and float for tristate. Keep

leakage currents under 1µA for robust tristate detection.

The SEL1-3 pins are de-bounced for 1.5ms for robust

transitions between USB states.

RT (Pin 9): RT is the switching frequency programming

pin. Tie a resistor from RT to ground to select the switch-

ing frequency. See the Applications Information section

for additional information.

SYNC/MODE (Pin 10): SYNC/MODE is the clock synchro-

nization and mode selection input pin. Ground SYNC/

MODE for pulse-skipping mode. Tie to a clock source

for synchronization to an external frequency and forced

continuous mode. Float for forced continuous mode with

RT programing the switching frequency. Tie to INTVCC for

forced continuous mode with spread-spectrum modula-

tion of the switching frequency for improved EMI/EMC

performance.

LD+ (Pin 12): LD+ is the low voltage host side of the

internal USB D+ dataline switch. Float this pin if not used.

LD– (Pin 13): LD– is the low voltage host side of the

internal USB D– dataline switch. Float this pin if not used.

HD– (Pin 15): HD– is the high voltage USB cable and

device side of the internal USB D– dataline switch. Both

dataline switches are disconnected if HD– > 4.5V. Float

this pin if not used.

HD+ (Pin 16): HD+ is the high voltage USB cable and

device side of the internal USB D+ dataline switch. Both

dataline switches are disconnected if HD+ > 4.5V. Float

this pin if not used.

CLAMP (Pin 18): Bypass CLAMP with a 0.1µF 20V or

greater low ESR capacitor to ground.

RCBL (Pin 19): RCBL is the cable drop compensation pro-

gramming pin. A resistor RCBL tied from RCBL to ground

programs the cable drop compensation by setting the

USB5V input current. RCBL can source 2mA. Excessive

capacitive loading on RCBL can degrade load transient

response. Isolate load capacitance on this pin by tying a

100k resistor between RCBL and the capacitive load. The

RCBL load monitor output is valid when the LT8698S is

enabled; otherwise the output is low. See the Applications

Information section for additional information.

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