ADAR2001ACCZ-R7 datasheet(15/39 Pages) AD

Nome de Peças	ADAR2001ACCZ-R7

Descrição Electrónicos	10 GHz to 40 GHz, 1:4 Channel, 4횞 Frequency Multiplier/Filter

PDF	39 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

Logo

15 / 39 page

Data Sheet

ADAR2001

Rev. 0 | Page 15 of 39

ADC AND ADC CLOCK

The ADAR2001 has an on-chip, 8-bit ADC and a variable clock

input, each with their own enable control bits.

To take a measurement from the ADC, the user must first write

to the ADC_CTRL register, Register 0x04A. This register

contains the following bits:

•

Bit 0: ADC_EOC (read only). This bit is a flag for when the

ADC conversion is done.

•

Bit 1 to Bit 3: MUX_SEL (read/write). These bits are used

to select the ADC input, according to Figure 27.

•

Bit 4: ST_CONV (read/write). This bit is set to start an

ADC conversion cycle.

•

Bit 5: CLK_EN (read/write). This bit enables the ADC

clock.

•

Bit 6: ADC_EN (read/write). This bit enables the ADC.

•

Bit 7: ADC_CLKFREQ_SEL (read/write). This bit sets the

clock frequency. A low sets the clock to 2 MHz, whereas a

high sets the clock to 250 kHz.

After the ADC_CTRL register is written, it must be polled to

wait for the ADC_EOC bit to go high. When this happens, the

measured value can be read out from the ADC_OUTPUT

ADAR2001ACCZ-R7 Folha de dados(PDF) 15 Page - Analog Devices