ADC32RF83 datasheet(63/138 Pages) TI

Nome de Peças	ADC32RF83

Descrição Electrónicos	ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

PDF	138 Pages

Scroll/Zoom	100%

Fabricante Electrônico	TI [Texas Instruments]

Página de início	http://www.ti.com

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63 / 138 page

tSDOUT

SCLK

SDOUT

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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Table 26. SPI Input Description

SPI BIT

DESCRIPTION

OPTIONS

R/W bit

Read/write bit

0 = SPI write

1 = SPI read back

M bit

SPI bank access

0 = Analog SPI bank (master)

1 = All digital SPI banks (main digital, interleaving,

decimation filter, JESD digital, and so forth)

P bit

JESD page selection bit

0 = Page access

1 = Register access

CH bit

SPI access for a specific channel of the JESD SPI

bank

0 = Channel A

1 = Channel B

ADDR[11:0]

SPI address bits

—

DATA[7:0]

SPI data bits

—

Figure 136 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT

bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.

Figure 136. SDOUT Timing

ADC32RF83 Folha de dados(PDF) 63 Page - Texas Instruments