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ADC32RF83 Folha de dados(PDF) 56 Page - Texas Instruments |
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ADC32RF83 Folha de dados(HTML) 56 Page - Texas Instruments |
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56 / 138 page  SYNCb SYSREF LMFC Clock LMFC Boundary xxx Transmit Data K28.5 K28.5 ILA ILA DATA DATA Multi Frame Code Group Synchronization Initial Lane Alignment Data Transmission 56 ADC32RF80, ADC32RF83 SBAS774A – MAY 2016 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Device Functional Modes (continued) 8.4.2.1 JESD204B Initial Lane Alignment (ILA) The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected on the SYNCB input, the ADC32RF8x starts transmitting comma (K28.5) characters to establish the code group synchronization, as shown in Figure 134. When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF8x starts the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF8x transmits four multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame start and end symbols. The second multiframe also contains the JESD204 link configuration data. Figure 134. JESD Internal Timing Information 8.4.2.2 JESD204B Frame Assembly The JESD204B standard defines the following parameters: • F is the number of octets per frame clock period • L is the number of lanes per link • M is the number of converters for the device • S is the number of samples per frame |
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