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STM32WB55CC Folha de dados(PDF) 127 Page - STMicroelectronics |
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STM32WB55CC Folha de dados(HTML) 127 Page - STMicroelectronics |
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127 / 165 page  DS11929 Rev 3 127/165 STM32WB55xx Electrical characteristics 152 6.3.20 Analog-to-Digital converter characteristics Unless otherwise specified, the parameters given in Table 73 are preliminary values derived from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions summarized in Table 22: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 73. ADC characteristics(1) (2) (3) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage - 1.62 - 3.6 V VREF+ Positive reference voltage VDDA ≥ 2 V 2 - VDDA V VDDA < 2 V VDDA V VREF- Negative reference voltage -VSSA V fADC ADC clock frequency Range 1 - - 64 MHz Range 2 - - 16 fs Sampling rate for FAST channels Resolution = 12 bits - - 4.26 Msps Resolution = 10 bits - - 4.92 Resolution = 8 bits - - 5.81 Resolution = 6 bits - - 7.11 Sampling rate for SLOW channels Resolution = 12 bits - - TBD Resolution = 10 bits - - TBD Resolution = 8 bits - - TBD Resolution = 6 bits - - TBD fTRIG External trigger frequency fADC = 64 MHz Resolution = 12 bits -- 4.26 MHz Resolution = 12 bits - - 15 1/fADC VCMIN Input common mode Differential mode (VREF++ VREF-) / 2 - 0.18 (VREF++ VREF-) / 2 (VREF++ VREF-) / 2 + 0.18 V VAIN (4) Conversion voltage range(2) -0 - VREF+ V RAIN External input impedance -- - 50 kΩ CADC Internal sample and hold capacitor -- 5 - pF tSTAB Power-up time - 1 Conversion cycle tCAL Calibration time fADC = 64 MHz 1.8125 µs - 116 1 / fADC |
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