STM32WB55CC datasheet(35/165 Pages) STMICROELECTRONICS

35 / 165 page

Stop 2

LPR

OFF

LSE,

LSI

RF, BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1, 2)

USART1(13)

LPUART1(13)

I2C3(10)

LPTIM1

All other peripherals are frozen.

Reset pin, all I/Os

RF, BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1, 2)

LPUART1

I2C3

LPTIM1

1.85 µA w/o RTC

2.1 µA w RTC

5.55 µs

Standby

LPR

OFF

SRAM2a

ON(11)

LSE,

LSI

RF, BOR, RTC, IWDG

All other peripherals are

powered off.

I/O configuration can be floating,

pull-up or pull-down

RF, Reset pin

5 I/Os (WKUPx)(12)

BOR, RTC, IWDG

0.32 µA w/o RTC

0.6 µA w RTC

TBD

OFF

TBD µA w/o RTC

TBD µA w RTC

Shutdown

OFF

LSE

RTC

All other peripherals are

powered off.

I/O configuration can be floating,

pull-up or pull-down(13)

5 I/Os (WKUPx)(12),

RTC

0.028 µA w/o RTC

0.315 µA w/ RTC

TBD

1. Typical current at VDD = 1.8 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.

2. Add TBD μs when using SMPS, except Sleep, LPSleep and Stop 0 where the SMPS is not stopped.

3. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.

4. Flash memory programming is only possible in Range 2 voltage.

5. Bluetooth® Low Energy not possible in this mode.

6. The SRAM1 and SRAM2 clocks can be gated off independently.

7. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.

8. HSI16 (16 MHz) automatically used by some peripherals.

9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.

10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

11. SRAM1 and SRAM2b are OFF.

12. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PC12, PA2, PC5.

13. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.

Table 8. STM32WB55xx modes overview (continued)

Mode

Regulator

CPU1

Flash

SRAM

Clocks

DMA and Peripherals

Wakeup source

Consumption(1)

Wakeup time(2)

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