MT7697DN datasheet(45/84 Pages) ETC2

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MT7697D

Internet-of-Things Wireless Connectivity

Page 45 of 84

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2, 4, 6, 8, 10, and 12MHz. It supports two options of clock polarity (CPOL) and two options of initial

clock phase (CPHA). SPI pins are multiplexed with I2S pins.

Table 2-17. SPI Pin Description

Signal Name

Signal Description

Direction

Chip select

Output

SCK

Serial clock

Output

MISO

Master in, Slave out

Input

MOSI

Master out, Slave in

Output

Figure 2-19. SPI Timing Diagram

2.5.6

SPI Slave Interface

2.5.7

I2S Interface

MT7697D features one I2S interface, which is used to connect to an external audio codec. The I2S

interface can support the I2S slave mode only. The five I2S signals are shown below. The I2S_MLK

clock frequency is 16MHz.

CS_N

SCK

(CPOL=0)

SCK Edge

Number

SCK

(CPOL=1)

10 11 12 13 14 15 16

SAMPLE MOSI/MISO

(CPHA=0)

SAMPLE MOSI/MISO

(CPHA=1)

Data Transmission

CS_N

idle time

CS_N setup time

CS_N hold time

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