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MT7697DN Folha de dados(PDF) 17 Page - List of Unclassifed Manufacturers

Nome de Peças MT7697DN
Descrição Electrónicos  Internet-of-Things Wireless Connectivity
PDF  84 Pages
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MT7697DN Folha de dados(HTML) 17 Page - List of Unclassifed Manufacturers

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MT7697D
Internet-of-Things Wireless Connectivity
© 2016 MediaTek Inc.
Page 17 of 84
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
2.3
Clock and Reset Generation
2.3.1
Clock
MT7697D connects to the XTAL or external clock source as the single clock source of the whole
system. The XTAL oscillator can support the XTAL frequencies from among 40, 26, and 52MHz.
XTAL
oscillator
f = 40/
26/52MHz
PLL1
DIV
PLL2
DIV 1
DIV 3
DIV 12
WF_RXADC_CLK
80MHz
WF_TXDAC_CLK
960MHz
WF_DIG_CLK
320MHz
32MHz
960MHz
DIV 5
SPI CLOCK
FLASH CLOCK
I2C CLOCK
UART CLOCK
XPLL (Audio Frac-N)
±1% (0.01% granularity)
I2S_MCLK
16MHz
AUXADC CLOCK
PWM CLOCK
DIV 13
2-32 step 0.5
1-160MHz
1-192MHz
832MHz
640MHz
RF PLL
WF RF
DIV 5
2-32 step 0.5
XTAL CLOCK
DIV
PMU
BGCLK
(25KHz)
F32K CLOCK
2MHz
0
0
0
0
1
1
DIV
DIV options:
480, 240, 120, 60,
30, 20, 15, 12, 10
9.6, 19.2, 38.4, 115.2KHz
DIV
DIV options: 2708,1354,677,226
DIV
50, 100, 200, 400KHz
DIV options: 520,260,130,65
N9 CLOCK
160MHz
DIV 8
DIV 794
CM4 CLOCK
192MHz
120MHz
250, 500KHz
1, 2, 4, 6, 8, 10, 12MHz
DIV
64MHz
DIV
16MHz
RF power domain
AON power domain
CM4 power domain
DIV 2
PMU power domain
830081B4[14:13]
0
1
2
80021114[21:20]
81021170[12:8]
830081B0[2:0]
1
4
1
3
830081B0[15:14]
830081B0[9:4]
81021100[2:0]
1
4
81021100[9:4]
830081B4[7:3]
1-32 step 1
0
1
3
81021100[15:14]
81021100[17:16]
81021100[31:21]
2
830081B4[17]
830081B4[23:19]
24000028[27:16]
830B0000[27:24]
2
830081B4[12:8]
8300A600[2:1]
2
0
83090244[15:0] 83090248[15:0]
830A0244[15:0]830A0248[15:0]
Figure 2-3. Clock Generation Block Diagram
PLL1 is used to generate the clock sources for Bluetooth and PLL2.
PLL2 is used to generate the clock sources for Wi-Fi, N9 core, Cortex-M4 core, and bus fabric.
XPLL is used to generate the clock sources for I2S (for external audio CODEC).



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