4052 datasheet(4/9 Pages) UTC

4 / 9 page

UTC 4052

CMOS

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

ELECTRICAL CHARACTERISTICS *5 (CL = 50 pF, TA = 25℃) (VEE ≤VSS unless otherwise indicated)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN TYP

MAX UNIT

Propagation Delay

Times(Figure 4)

Switch Input to Switch

Output

tPLH,tPHL RL=10kΩ

VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns

VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns

VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns

Propagation Delay

Times(Figure 4)

Inhibit to Output

tPHZ,tPLZ

tPZH,tPZL

RL=10kΩ,VEE=Vss

Output”1” or “0” to High Impedance, or

High Impedance to”1” or “0” Level

VDD-VEE= 5.0

VDD-VEE=10

VDD-VEE=15

300

155

125

600

310

250

Propagation Delay

Times(Figure 4)

Control Input to Output

tPLN,tPHL RL=10kΩ,VEE=Vss

VDD-VEE= 5.0

VDD-VEE=10

VDD-VEE=15

325

130

650

260

180

Second Harmonic

Distortion

RL=10kΩ, f=1kHz, Vin=5Vpp,

VDD-VEE=10

0.07

Bandwidth (Figure 5)

RL=1kΩ, Vin=1/2(VDD-VEE)p-p, CL=50pF,

20 Log (Vout/Vin)=-3dB,

VDD-VEE=10

MHz

Off Channel

Feedthrough Attenuation

(Figure 5)

RL=1kΩ, Vin=1/2(VDD-VEE)p-p, Fin=30MHz,

VDD-VEE=10

-50

Channel Separation

(Figure 6)

RL=1kΩ, Vin=1/2(VDD-VEE)p-p, fin=3.0MHz

VDD-VEE=10

-50

Crosstalk ,Control Input

to Common O/I (Figure

R1=1kΩ, RL=10kΩ,

Control tTLH=tTHL=20ns ,Inhibit=Vss),

VDD-VEE=10

*5. The formulas given are for the typical characteristics only at 25 ℃.

*6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential

*performance.

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