4052 datasheet(3/9 Pages) UTC

3 / 9 page

UTC 4052

CMOS

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R502-013,A

-55°C

25°C

125°C

PARAMETER

SYMBOL

TEST CONDITIONS

MIN MAX MIN TYP*3 MAX MIN MAX

UNIT

Input Leakage

Current

Iin

VDD=15V ,Vin=0 or VDD

0.1

10-5 ±0.1

1.0

µA

Input Capacitance

Cin

5.0

7.5

SWITCHES IN/OUT AND COMMONS OUT/IN –X,Y,Z(Voltages Referenced to VEE)

Recommended

Peak-to-Peak

Voltage Into or Out of

the Switch

VI/O

Channel On or Off

VDD

Vpp

Recommended Static

or Dynamic Voltage

Across the Switch *4

(Figure 3)

△

Vswitch Channel On

600

300

Output Offset

Voltage

Voo

Vin=0V,No Load

µV

ON Resistance

Ron

△

Vswitch≤500mV *4

Vin=VIL or VIH (Control),

and Vin=0 to VDD(Switch)

VDD=5.0V

VDD=10V

VDD=15V

800

400

220

250

120

1050

500

280

1200

520

300

△

ON Resistance

Between Any Two

Channels in the

Same Package

△

Ron

VDD=5.0V

VDD=10V

VDD=15V

135

Off-Channel Leakage

Current(Figure 8)

Ioff

VDD=15V ,Vin=VIL or VIH

(Control) Channel to

Channel or Any One

Channel

100

0.05 ±100

1000

Capacitance,

Switch I/O

CI/O

Inhibit=VDD

Capacitance,

Common O/I

CO/I

Inhibit=VDD

Capacitance,

Feedthrough

(Channel Off)

CI/O

Pins Not Adjacent

Pins Adjacent

0.15

0.47

*3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential

*performance.

*4. For voltage drops across the switch (△Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD

current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The

*reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data

*sheet.)

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