AM652X datasheet(277/299 Pages) TI1

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AM6548, AM6528, AM6546

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Detailed Description

•

Clock Multiplying Unit (CMU)

–

PLLs

–

Master bias

–

Termination calibration

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Reference clock input buffers

•

Physical Coding Sub-block (PCS)

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8b/10b encoder/decoder (PCIe 1 and PCIe 2)

–

128b/130b encoder/decoder (PCIe 3)

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Symbol alignment

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Polarity inversion

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Bit stream reordering

•

Physical Media Attachment (PMA) layer

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Transmit equalization

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Receive equalization

The SERDES mux (WIZ) module supports the following features:

•

Multiplexes device interfaces onto a single SERDES lane (one Tx and one Rx)

•

Provides registers to implement SERDES control and status functions and alignment delays

•

Clock generator block for providing MAC transmit clock

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Rx comma align block

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Performs de-stuffing the Rx data stream in the event that the Rx rate is different from the Tx rate

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Supports comma detection that is not sensitive to false commas using all 8B10B character

combinations

For more information, see section Serializer/Deserializer (SerDes) in chapter Peripherals of the device

TRM.

6.11.24 Timers

There are sixteen timer modules in the device.

All timers include specific functions to generate accurate tick interrupts to the operating system.

Each timer can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz clock. The selection

of clock source is made from registers in the MCU_CTRL_MMR0/CTRL_MMR0.

In the MCU domain the device provides 2 timer pins to be used as MCU Timer Capture inputs or as MCU

Timer PWM outputs. In order to provide maximum flexibility, these 2 pins may be used with any of

MCU_TIMER0 through MCU_TIMER3 instances. System level muxes are used to control the capture

source pin for each MCU_TIMER[3-0] and the MCU_TIMER[3-0] source for each MCU_TIMER_IO[1-0]

PWM output.

In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer

PWM outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER11

instances. System level muxes are used to control the capture source pin for each TIMER[11-0] and the

TIMER[11-0] source for each TIMER_IO[7-0] PWM output.

Each odd numbered timer instance from each of the domains may be optionally cascaded with the

previous even numbered timer instance from the same domain to form up to a 64-bit timer. For example,

TIMER1 may be cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.

When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-

bit prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output

edge at the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.

For more information, see section Timers in chapter Peripherals of the device TRM.

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