AM652X datasheet(279/299 Pages) TI1

279 / 299 page

279

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

Selectable bit rate

•

Configurable carrier frequency

•

1/2, 5/12, 1/3, or 1/4 carrier duty cycle

•

CIR mode when 48 MHz function clock is used

UART Not Supported Features:

•

Synchronous mode

•

ISO7816 mode

For more information, see section Universal Synchronous/Asynchronous Receiver/Transmitter (UART) in

chapter Peripherals of the device TRM.

6.11.26 USB

Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange

between a host device and a wide range of simultaneously accessible peripherals.

The device supports two USB subsystems, both instantiated in the MAIN system domain:

•

USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS

(USB3.0) PHY and HS/FS (USB2.0) PHY

•

USB3SS1 is HighSpeed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS

(USB2.0) PHY

The USB subsystem, supports the following USB features:

•

General features:

–

Supports Peripheral (aka Device) mode at Superspeed (5 Gbps), Highspeed (480 Mbps), and

Fullspeed (12 Mbps)

–

Supports Host mode at Superspeed (5 Gbps), Highspeed (480 Mbps), Fullspeed (12 Mbps), and

Lowspeed (1.5 Mbps)

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Static peripheral operation

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Static host operation

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Limited OTG 2.0 functionality in conjunction with an VBUS/ID analog comparator detection circuit

and software handshake

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Host Negotiation Protocol (HNP) support in conjunction with an ID comparator detection circuit and

software handshake

–

Accessory Charger Adapter (ACA) support via ID-pin comparator

–

External Buffer Control (EBC) mode for IN (Tx) Endpoints 14 and 15

•

Each controller instance contains single xHCI with the following features:

–

Compatible to the xHCI specification (revision 1.1) in Host mode

–

Supports 15 Transmit (TX), 15 Receive (RX) endpoints (EPs), and one EP0 endpoint which is

bidirectional

–

Internal DMA controller

–

Interrupt moderation and blocking

–

Supports for all USB transfer modes - Control, Bulk, Interrupt, and Isochronous

–

Supports high bandwidth ISO mode

–

Descriptor caching and data pre-fetching used to improve system performance

–

Dynamic FIFO memory allocation for all endpoints

–

USB power saving states (U0, U1, U2, and U3)

–

Asynchronous wakeup signal for remote wakeup

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