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AM652X Folha de dados(PDF) 281 Page - Texas Instruments |
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AM652X Folha de dados(HTML) 281 Page - Texas Instruments |
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281 / 299 page ![]() A B MCU_OSPI[x]_CLK R1 OSPI/QSPI/SPI device clock input OSPI/QSPI/SPI device IOy, CS# MCU_OSPI[x]_D[y], MCU_OSPI[x]_CSn[z] 0 * Ω OSPI_Board_01 281 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Applications, Implementation, and Layout Copyright © 2017–2018, Texas Instruments Incorporated 7 Applications, Implementation, and Layout NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test design implementation to confirm system functionality. 7.1 DDR Board Design and Layout Guidelines The goal of the DDR3L, DDR4, and LPDDR4 Board Design and Layout Guidelines Application Report (SPRACI2) is to make the DDR3L, DDR4, and LPDDR4 system implementation straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports board designs using DDR3L, DDR4, and LPDDR4 memories that follow the guidelines in this document. 7.2 OSPI Board Design and Layout Guidelines The following section details the routing guidelines that must be observed when routing the OSPI interfaces. 7.2.1 No Loopback & Internal Pad Loopback • The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device • The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450pS (~7cm as stripline or ~8cm as microstrip) • 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-1 • Propagation delays and matching: – A to B < 450ps – Matching skew: < 60pS Figure 7-1. OSPI Interface High Level Schematic NOTE *0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed. |
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