AM652X datasheet(216/299 Pages) TI1

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OSPI_DQS

OSPI_D[i:0]

O16

O15

OSPI_TIMING_04

OSPI_CLK

OSPI_D[i:0]

O14

O13

OSPI_TIMING_03

216

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Specifications

Table 5-89. OSPI Timing Requirements - DDR Mode (1) (continued)

NO.

PARAMETE

DESCRIPTION

MODE

MIN

MAX

UNIT

O17

tsu(D-DQS)

Setup time, DQS edge to D[i:0] transition

1.8V, OSPI0 DQS;

1.8V, OSPI1 DQS

-0.46

3.3V, OSPI0 DQS;

3.3V, OSPI1 DQS

-0.66

O18

th(DQS-D)

Hold time, DQS edge to D[i:0] transition

1.8V, OSPI0 DQS;

1.8V, OSPI1 DQS

3.59

3.3V, OSPI0 DQS;

3.3V, OSPI1 DQS

7.92

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC

and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external

loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.

Figure 5-94. OSPI Timing Requirements - DDR, No Loopback Clock and Internal Pad Loopback Clock

Figure 5-95. OSPI Timing Requirements - DDR, External Loopback Clock and DQS

Table 5-90. OSPI Timing Requirements - SDR Mode (1)

NO.

PARAMET

DESCRIPTION

MODE

MIN

MAX

UNIT

O19

tsu(D-CLK)

Setup time, D[i:0] valid before active CLK

edge

1.8V, No Loopback Clock

-2.18

3.3V, No Loopback Clock

-1.7

O20

th(CLK-D)

Hold time, D[i:0] valid after active CLK edge

1.8V, No Loopback Clock

7.62

3.3V, No Loopback Clock

8.1

O21

tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK

input (DQS) edge

1.8V, External Board Loopback Clock

-3.24

3.3V, External Board Loopback Clock

-2.72

O22

th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK

input (DQS) edge

1.8V, External Board Loopback Clock

3.81

3.3V, External Board Loopback Clock

4.33

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