AM652X datasheet(215/299 Pages) TI1

215 / 299 page

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

215

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

Table 5-88. OSPI Switching Characteristics - SDR Mode (1) (continued)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O11

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

-1+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

1+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

3.3V

-1+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

1+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

O12

td(CLK-D)

Delay time, CLK active edge to D[i:0] transition

1.8V

-1.15

1.25

3.3V

-1.33

1.51

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) P = CLK cycle time

(3) P = SCLK period

(4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(5) R = refclk

Figure 5-93. OSPI Switching Characteristics - SDR

Table 5-89, Table 5-90, Figure 5-94, Figure 5-95, Figure 5-96, and Figure 5-97 presents timing

requirements for OSPI DDR and SDR Mode.

Table 5-89. OSPI Timing Requirements - DDR Mode (1)

NO.

PARAMETE

DESCRIPTION

MODE

MIN

MAX

UNIT

O13

tsu(D-CLK)

Setup time, D[i:0] valid before active CLK edge

1.8V, No Loopback Clock;

1.8V, Internal Pad Loopback

Clock

5.23

3.3V, No Loopback Clock;

3.3V, Internal Pad Loopback

Clock

6.19

O14

th(CLK-D)

Hold time, D[i:0] valid after active CLK edge

1.8V, No Loopback Clock;

1.8V, Internal Pad Loopback

Clock

1.84

3.3V, No Loopback Clock;

3.3V, Internal Pad Loopback

Clock

2.34

O15

tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK (DQS)

edge

1.8V, External Board

Loopback Clock

0.52

3.3V, External Board

Loopback Clock

1.97

O16

th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK (DQS)

edge

1.8V, External Board

Loopback Clock

1.8 (2)

3.3V, External Board

Loopback Clock

2.2 (2)

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