AM652X datasheet(214/299 Pages) TI1

214 / 299 page

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_01

OSPI_CSn

214

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Specifications

Table 5-87. OSPI Switching Characteristics - DDR Mode (1) (continued)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

td(CLK-CSn)

Delay time, CLK rising edge to CSn active edge 1.8V, OSPI0 DDR TX;

1.8V, OSPI1 DDR TX

-7.7-0.475 *

P – 0.975 * N

* R (3) (4) (5)

0-0.475 * P –

0.975 * N * R

(3) (4) (5)

3.3V, OSPI0 DDR TX;

3.3V, OSPI1 DDR TX

-8-0.475 *

P – 0.975 * N

* R (3) (4) (5)

0-0.475 * P –

0.975 * N * R

(3) (4) (5)

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V, OSPI0 DDR TX;

1.8V, OSPI1 DDR TX

-7.7+0.475 *

P + 0.975 * N

* R (3) (4) (5)

0+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

3.3V, OSPI0 DDR TX;

3.3V, OSPI1 DDR TX

-8+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

0+0.475 * P

+ 0.975 * N *

R (3) (4) (5)

td(CLK-D)

Delay time, CLK active edge to D[i:0] transition

1.8V, OSPI0 DDR TX;

1.8V, OSPI1 DDR TX

-7.7

-1.56

3.3V, OSPI0 DDR TX;

3.3V, OSPI1 DDR TX

-7.7

-1.56

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) P = CLK cycle time

(3) P = SCLK period

(4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(5) R = refclk

Figure 5-92. OSPI Switching Characteristics - DDR

Table 5-88. OSPI Switching Characteristics - SDR Mode (1)

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

7.52

tw(CLKL)

Pulse duration, CLK low

-0.3+0.475*P

(2)

tw(CLKH)

Pulse duration, CLK high

-0.3+0.475*P

(2)

O10

td(CLK-CSn)

Delay time, CLK rising edge to CSn active edge

1.8V

-1-0.475 *

P – 0.975 * N

* R (3) (4) (5)

1-0.475 * P –

0.975 * N * R

(3) (4) (5)

3.3V

-1-0.475 *

P – 0.975 * N

* R (3) (4) (5)

1-0.475 * P –

0.975 * N * R

(3) (4) (5)

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