LTC1735 datasheet(21/32 Pages) LINER

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LTC3728L-1

3728l1fc

APPLICATIONS INFORMATION

pulling up the PLLFLTR pin. When the external frequency is

less than f0SC, current is sunk continuously, pulling down

the PLLFLTR pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. Thus the voltage on the PLLFLTR pin

is adjusted until the phase and frequency of the external

and internal oscillators are identical. At this stable operat-

ing point the phase comparator output is open and the

ﬁlter capacitor CLP holds the voltage. The IC’s PLLIN pin

must be driven from a low impedance source such as a

logic gate located close to the pin. When using multiple

ICs for a phase-locked system, the PLLFLTR pin of the

master oscillator should be biased at a voltage that will

guarantee the slave oscillator(s) ability to lock onto the

master’s frequency. A DC voltage of 0.7V to 1.7V applied

to the master oscillator’s PLLFLTR pin is recommended

in order to meet this requirement. The resultant operating

frequency can range from 300kHz to 500kHz.

The loop ﬁlter components (CLP, RLP) smooth out the cur-

rent pulses from the phase detector and provide a stable

input to the voltage controlled oscillator. The ﬁlter compo-

nents CLP and RLP determine how fast the loop acquires

lock. Typically RLP =10kΩ and CLP is 0.01μF to 0.1μF.

Minimum On-Time Considerations

Minimum on-time tON(MIN)isthesmallesttimedurationthat

each controller is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

tON(MIN) <

VOUT

VIN(f)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for each controller is approximately

100ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about 150ns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a signiﬁcant amount of cycle skipping can occur with cor-

respondingly larger current and voltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding

or as a logic level input. Continuous operation is forced

on both controllers when the FCB pin drops below 0.8V.

During continuous mode, current ﬂows continuously in

the transformer primary. The secondary winding(s) draw

current only when the bottom, synchronous switch is on.

When primary load currents are low and/or the VIN/VOUT

ratio is low, the synchronous switch may not be on for a

sufﬁcient amount of time to transfer power from the output

capacitor to the secondary load. Forced continuous opera-

tion will support secondary windings providing there is

sufﬁcient synchronous switch duty factor. Thus, the FCB

input pin removes the requirement that power must be

drawn from the inductor primary in order to extract power

from the auxiliary windings. With the loop in continuous

mode, the auxiliary outputs may nominally be loaded

without regard to the primary output load.

The secondary output voltage VSECisnormallysetasshown

in Figure 6a by the turns ratio N of the transformer:

VSEC ≅ (N + 1) VOUT

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current, then

VSEC will droop. An external resistive divider from VSEC to

the FCB pin sets a minimum voltage VSEC(MIN):

VSEC(MIN) 0.8V 1+

where R5 and R6 are shown in Figure 2.

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