LTC1735 datasheet(20/32 Pages) LINER

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LTC3728L-1

3728l1fc

APPLICATIONS INFORMATION

ent temperature, conditions that cause the highest power

dissipation in the top MOSFET.

Each controller includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch described above is overridden. If the

output falls below 70% of its nominal output level, then

the maximum sense voltage is progressively lowered from

75mV to 17mV. Under short-circuit conditions with very

low duty cycles, the controller will begin cycle skipping

in order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time tON(MIN)

of each controller (typically 100ns), the input voltage and

inductor value:

ΔIL(SC) = tON(MIN) (VIN/L)

The resulting short-circuit current is:

ISC =

25mV

RSENSE

–

IL(SC)

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

much higher than nominal levels. The crowbar causes huge

currents to ﬂow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the controller

is operating.

A comparator monitors the output for overvoltage con-

ditions. The comparator (OV) detects overvoltage faults

greater than 7.5% above the nominal output voltage. When

this condition is sensed, the top MOSFET is turned off and

the bottom MOSFET is turned on until the overvoltage

condition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and will

therefore allow a switching regulator system having a poor

PC layout to function while the design is being debugged.

The bottom MOSFET remains on continuously for as long

as the OV condition persists; if VOUT returns to a safe level,

normal operation automatically resumes. A shorted top

MOSFET will result in a high current condition which will

open the system fuse. The switching regulator will regulate

properly with a leaky top MOSFET by altering the duty

cycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This al-

lows the top MOSFET turn-on to be locked to the rising

edge of an external source. The frequency range of the

voltage controlled oscillator is ± 50% around the center

frequency fO. A voltage of 1.2V applied to the PLLFLTR

pin corresponds to a frequency of approximately 400kHz.

The nominal operating frequency range of the IC is 260kHz

to 550kHz.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the ex-

ternal and internal oscillators. This type of phase detector

will not lock up on input frequencies close to the harmonics

of the VCO center frequency. The PLL hold-in range, ΔfH,

is equal to the capture range, ΔfC:

ΔfH = ΔfC = ±0.5 fO (260kHz-550kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

ﬁlter network on the PLLFLTR pin.

If the external frequency (fPLLIN) is greater than the os-

cillator frequency f0SC, current is sourced continuously,

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