DS3154 datasheet(18/60 Pages) DALLAS

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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RCRn

Receiver Configuration Register

02h, 12h, 22h, 32h

Bit

Name

ITU

RBIN

RCINV

RJA

RPD

RTS

RMON

RCVUD

Default

Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations

on the RLCV pin and counted in the RCV register. It also controls whether or not excessive zero (EXZ) events are

flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth

consecutive zero (E3 mode) in a sequence of zeros.

0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and

counted. EXZ events are also flagged and counted.

1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3

mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not

flagged and counted in any mode.

Bit 6: Receiver Binary Interface Enable (RBIN)

0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is

disabled.

1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations.

The B3ZS/HDB3 encoder is enabled.

Bit 5: Receiver Clock Invert (RCINV)

0 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK.

1 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK.

Bit 4: Receiver Jitter Attenuator Enable (RJA). (Note that TJA = 1 takes precedence over RJA = 1.)

0 = remove jitter attenuator from the receiver path

1 = insert jitter attenuator into the receiver path

Bit 3: Receiver Power-Down Enable (RPD)

0 = enable the receiver

1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated)

Bit 2: Receiver Tri-State Enable (RTS). This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT,

RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The

RTS pin is inverted and logically

ORed with this bit.

0 = enable the receiver outputs

1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK)

Bit 1: Receiver Monitor Preamp Enable (RMON)

0 = disable the monitor preamp

1 = enable the monitor preamp

Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the

RCVLn and RCVHn registers are loaded with the current code-violation count, and the internal code-violation

counter is cleared.

®1 = Update RCV registers and clear internal code-violation counter

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