MB90F548GPF datasheet(53/70 Pages) CYPRESS

53 / 70 page

Document Number: 002- 07696 Rev. *A

Page 53 of 70

MB90540G/545G Series

11.4.8 Hold Timing

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC

 3.5 V to 5.5 V, V

 AV

 0.0 V, T

  40 C to  105 C)

(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC

 5.0 V  10, V

 AV

 0.0 V, T

  40 C to  105 C)

Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.

11.4.9 UART0/1, Serial I/O Timing

(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC

 3.5 V to 5.5 V, V

 AV

 0.0 V, T

  40 C to  105 C)

(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC

 5.0 V  10, V

 AV

 0.0 V, T

  40 C to  105 C)

Notes :

■ AC characteristic in CLK synchronized mode.

■ CL is load capacity value of pins when testing.

■ For tCP (Machine clock cycle time) , refer to “ (1) Clock Timing”.

Parameter

Symbol

Pin name

Condition

Value

Units

Remarks

Min

Max

Pin floating

 HAK time

tXHAL

HAK



tCP

HAK

 time  Pin valid time

tHAHV

HAK

tCP

2 tCP

Parameter

Symbol

Pin name

Condition

Value

Units

Remarks

Min

Max

Serial clock cycle time

tSCYC

SCK0 to SCK2

Internal clock operation

output pins are CL

 80

 1 TTL.

8 tCP



SCK

  SOT delay time

tSLOV

SCK0 to SCK2,

SOT0 to SOT2

 80 80

Valid SIN

 SCK

tIVSH

SCK0 to SCK2,

SIN0 to SIN2

100



SCK

 Valid SIN hold time

tSHIX

SCK0 to SCK2,

SIN0 to SIN2



Serial clock “H” pulse width

tSHSL

SCK0 to SCK2

External clock operation

output pins are CL

 80

 1 TTL.

4 tCP



Serial clock “L” pulse width

tSLSH

SCK0 to SCK2

4 tCP



SCK

  SOT delay time

tSLOV

SCK0 to SCK2,

SOT0 to SOT2



150

Valid SIN

 SCK

tIVSH

SCK0 to SCK2,

SIN0 to SIN2



SCK

  Valid SIN hold time

tSHIX

SCK0 to SCK2,

SIN0 to SIN2



HAK

tXHAL

tHAHV

2.4 V

0.8 V

2.4 V

0.8 V

Each pin

High impedance

 Hold Timing

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