BQ25708 datasheet(4/77 Pages) TI1

4 / 77 page

VBUS

HIDRV2

ACN

SW2

ACP

VSYS

CHRG_OK

BATDRV

SRP

ILIM_HIZ

SRN

VDDA

CELL_BATPRESZ

IADPT

COMP2

bq25708

SLUSCU2 – NOVEMBER 2017

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6 Pin Configuration and Functions

RSN Package

32-Pin WQFN

Top View

Pin Functions

I/O

DESCRIPTION

NAME

NUMBER

ACN

PWR

Input current sense resistor negative input. The leakage on ACP and ACN are matched. The

series resistors on the ACP and ACN pins are placed between sense resistor and filter cap.

Refer to Application and Implementation for ACP/ACN filter design.

ACP

PWR

Input current sense resistor positive input. The leakage on ACP and ACN are matched. The

series resistors on the ACP and ACN pins are placed between sense resistor and filter cap.

Refer to Application and Implementation for ACP/ACN filter design.

BATDRV

P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the

BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to

regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on

during fast charge and supplement mode.

BTST1

PWR

Buck mode high side power MOSFET driver power supply. Connect a 0.047-µF capacitor

between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated.

BTST2

PWR

Boost mode high side power MOSFET driver power supply. Connect a 0.047-μF capacitor

between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated.

CELL_BATPRESZ

Battery cell selection pin for 1–4 cell battery setting. CELL_BATPRESZ pin is biased from

VDDA. CELL_BATPRESZ pin also sets SYSOVP threshold to 5 V for 1-cell, 12 V for 2-cell ,

and 19.5 for 3-cell/4-cell. CELL_BATPRESZ pin is pulled below VCELL_BATPRESZ_FALL to

indicate battery removal. The device exits LEARN mode, and disables charge. REG0x15()

goes back to default.

CHRG_OK

Open drain active high indicator to inform the system good power source is connected to the

charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or

falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS is falls below

3.2V or rises above 26V, CHRG_OK is LOW.

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