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AD6673

Data Sheet

Rev. C | Page 32 of 45

Bit

Bit Name

Description

Realign on SYSREF±;

for Subclass 1 only

When this bit is set to 1 and an active SYSREF signal occurs, the internal clock alignment for the JESD204B

timing is forced. Setting this bit is only recommended for one-shot mode and must be done only prior to

initially establishing a link. This bit resets the JESD204B link on the active SYSREF signal and requires

additional clock alignment register writes after realignment to properly set up the timing margin over

temperature. See the Synchronization section for the clock alignment procedure. For continuous SYSREF±

mode, this bit must be set to 0 during normal operation.

Realign on

SYNCINB±; for

Subclass 1 only

When this bit is set to 1 and an active SYNC occurs, the internal clock alignment for the JESD204B timing is

forced. An active SYNC requires an SYNCINB± input to be logic low for at least four consecutive LMFCs.

Table 15. AD6673 JESD204B Frame Alignment Monitoring and Correction Replacement Characters

Scrambling

Lane Synchronization

Character to be Replaced

Last Octet in

Multiframe

Replacement Character

Off

Last octet in frame repeated from previous frame

K28.7

Off

Last octet in frame repeated from previous frame

Yes

K28.3

Off

Last octet in frame repeated from previous frame

Not applicable

K28.7

Last octet in frame equals D28.7

K28.7

Last octet in frame equals D28.3

Yes

K28.3

Off

Last octet in frame equals D28.7

Not applicable

K28.7

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the JESD204B

specification. The 11-bit word requires two octets to transmit all

the data. The two octets (MSB and LSB), where F = 2, make up

a frame. During normal operating conditions, frame alignment

is monitored via alignment characters, which are inserted under

certain conditions at the end of a frame. Table 15 summarizes the

conditions for character insertion along with the expected characters

under the various operation modes. If lane synchronization is

enabled, the replacement character value depends on whether

the octet is at the end of a frame or at the end of a multiframe.

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replacement characters.

Digital Outputs and Timing

The AD6673 has differential digital outputs that power up by

default. The driver current is derived on-chip and sets the output

current at each output equal to a nominal 4 mA. Each output

presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 300 mV peak-to-peak swing at

the receiver (see Figure 52). Alternatively, single-ended 50 Ω

termination can be used. When single-ended termination is

used, the termination voltage should be DRVDD/2; otherwise,

ac coupling capacitors can be used to terminate to any single-

ended voltage.

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUTx+

DRVDD

VRXCM

SERDOUTx–

VCM = Rx VCM

0.1µF

RECEIVER

OUTPUT SWING = VOD

(SEE TABLE 3)

Figure 52. AC-Coupled Digital Output Termination Example

The AD6673 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common

mode of the digital output automatically biases itself to half the

supply of the receiver (that is, the common-mode voltage is 0.9 V

for a receiver supply of 1.8 V) if dc-coupled connecting is used

(see Figure 53). For receiver logic that is not within the bounds

of the DRVDD supply, use an ac-coupled connection. Simply

place a 0.1 µF capacitor on each output pin and derive a 100 Ω

differential termination close to the receiver side.

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

VCM = DRVDD/2

OUTPUT SWING = VOD

(SEE TABLE 3)

RECEIVER

SERDOUTx+

SERDOUTx–

Figure 53. DC-Coupled Digital Output Termination Example

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