ADAU1772BCPZ-R7 datasheet(57/117 Pages) AD

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ADAU1772

Data Sheet

Rev. C | Page 56 of 116

Bits

Bit Name

Settings

Description

Reset

Access

[2:1]

PLL input clock divide ratio.

0x0

Pin clock input/1

Pin clock input/2

Pin clock input/3

Pin clock input/4

PLL_TYPE

PLL type.

0x0

Integer

Fractional

PLL LOCK FLAG REGISTER

Address: 0x0006, Reset: 0x00, Name: PLL_CTRL5

Table 36. Bit Descriptions for PLL_CTRL5

Bits

Bit Name

Settings

Description

Reset

Access

LOCK

Flag to indicate if the PLL is locked. This bit is read only.

0x0

PLL unlocked

PLL locked

CLKOUT SETTING SELECTION REGISTER

Address: 0x0007, Reset: 0x00, Name: CLKOUT_SEL

When Pin ADC_SDATA1/CLKOUT/MP6 is set to clock output mode, the frequency of the output clock is set here. CLKOUT can be used

to provide a master clock to another IC, the clock for digital microphones, or as the clock for the PDM output stream. The 12 MHz/24

MHz setting is used when clocking another IC, 3 MHz/6 MHz for PDMOUT, and 1.5 MHz/3 MHz when clocking digital microphones.

The CLKOUT frequency is derived from the master clock frequency, which is assumed to (and always should) be 12.288 MHz. The

12.288 MHz and 24.576 MHz output modes are not functional if PDM is enabled (Register PDM_OUT, Bits[1:0]).

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