AD6652BBC datasheet(13/76 Pages) AD

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AD6652

Rev. 0 | Page 13 of 76

Pin No.

Mnemonic

Type

Function

DDC OUTPUTS

B11

LIA

Output

Level Indicator, Input A, Data A.

C11

LIA

Output

Level Indicator, Input A, Data A.

C12

LIB

Output

Level Indicator, Input B, Data B.

LIB

Output

Level Indicator, Input B, Data B.

PACH0_LACLKOUT2

Output

Channel ID Output Bit, LSB, for Parallel Port A, or Link Port A Clock Output.

Function depends on logic state of 0x1B:7 of output port control register.

PACH0_LBCLKOUT2

Output

Channel ID Output Bit, LSB, for Parallel Port B, or Link Port B Clock Output.

Function depends on logic state of 0x1D:7 of output port control register.

F1, D1, D2,

C2, B2, E2,

A4, A2

PA[7:0]_LA[7:0]

Output

Link Port A Data or Parallel Port A Data [7:0], Eight Pins.

P2, R3, N3,

M2, M3, T3,

L1, L2

PB[7:0_LB[7:0]

Output

Link Port B Data or Parallel Port B Data [7:0], Eight Pins.

E1, C1, F3,

G2, G1, G3,

H3, H2

PA[15:8]

Output

Parallel Port A Data [15:8], Eight Pins.

P3, R4, P4,

T4, R5, T5,

P5, R6

PB[15:8]

Output

Parallel Port B Data [15:8], Eight Pins.

PAIQ

Output

Parallel Port A I or Q Data Indicator, I = High, Q = Low.

PBIQ

Output

Parallel Port B I or Q Data Indicator, I = High, Q = Low.

PARALLEL OUTPUT PORT CONTROL

PAACK

Input

Parallel Port A Acknowledge.

PAREQ

Output

Parallel Port A Request.

PBACK

Input

Parallel Port B Acknowledge.

PBREQ

Output

Parallel Port B Request.

MICROPORT CONTROL

C5, A5, C6,

A6, B7, C7,

B8, C8

D[7:0]

I/O

Bidirectional Microport Data, Eight Pins. This bus is three-stated when CS is high.

B4, C3, A3

A[2:0]

Input

Microport Address Bus, 3 Pins.

DS(RD)4

Input

Function depends upon MODE pin.

Active Low Data Strobe when MODE = 1.

Active Low Read Strobe when MODE = 0.

DTACK(RDY)4, 5

Output

Function depends upon MODE pin.

Active Low Data Acknowledge when MODE = 1.

Microport Status Pin when MODE = 0.

R/W (WR)4

Input

Read/Write Strobe when MODE = 1. Active Low Write strobe when MODE = 0.

MODE4

Input

Mode Select Pin. 0 = Intel mode, 1 = Motorola mode.

CS3

Input

Active Low Chip Select. Logic 1 three-states the microport data bus.

1 PDWN pins must be the same logic level: both logic high or both logic low.

2 PACH0 and PACH1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0, 1, 2, or 3) whose data appears on Port A parallel

outputs. Likewise, PBCH0 and PBCH1 identify the channel for Port B.

3 Pins with a pull-down resistor of nominal 70 kΩ.

4 Mode 0 is Intel nonmultiplexed (IMN), and Mode 1 is Motorola nonmultiplexed (MNM). Pin logic level corresponds to mode.

5 Pins with a pull-up resistor of nominal 70 kΩ.

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