R80515 Megafunction Datasheet

Verification Methods

The R80515 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus

was applied to a hardware model that contained the original Intel 80C31 and Siemens SAB80C537 chips, and the

results were compared with the core’s simulation outputs.

Device Utilization & Performance

Supported

Device

Utilization

Performance

Family

Tested

LEs

Memory

Memory bits

Cyclone

EP1C4-6

3696

3 M4K

10,240

38 MHz

Stratix

EP1S10-5

3726

3 M4K

10,752

39 MHz

Stratix-II

EP2S5-3

3115

3 M4K

10,752

51 MHz

Notes:

1.

Optimized for speed

Deliverables

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VHDL or Verilog HDL source code

Post-synthesis EDIF netlist (netlist license)

Testbench (self-checking)

Vectors for testing the core

Place & route scripts (netlist license)

Simulation script

Synthesis script

Documentation

Contact Information

CAST, Inc.

11 Stonewall Court

Woodcliff Lake, New Jersey 07677 USA

Phone: +1 201-391-8300

Fax:

+1 201-391-8694

E-Mail: info@cast-inc.com

URL:

www.cast-inc.com

This megafunction developed by the

processor experts at

Evatronix SA

Copyright © CAST, Inc. 2004, All Rights Reserved. Contents subject to change without notice

CAST, Inc.

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