AS8C803601 datasheet(6/21 Pages) ALSC

6 / 21 page

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with

ZBT™

™

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings(1)

Pin Configuration - 512K x 18

119 BGA Capacitance(1)

(TA = +25° C, f = 1.0MHz)

Top View

100 TQFP

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VDD terminals only.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;

however, the voltage on any input or I/O pin cannot exceed V DDQ during power

supply ramp up.

7. During production testing, the case temperature equals T A.

NOTE:

1. This parameter is guaranteed by device characterization, but not production tested.

Symbol

Rating

Commercial &

Industrial

Unit

VTERM(2)

Terminal Voltage with

Respectto GND

-0.5 to +4.6

VTERM(3,6)

Terminal Voltage with

Respectto GND

-0.5 to VDD

VTERM(4,6)

Terminal Voltage with

Respectto GND

-0.5 to VDD +0.5

VTERM(5,6)

Terminal Voltage with

Respectto GND

-0.5 to VDDQ +0.5

TA(7)

Commercial

Operating Temperature

-0 to +70

Industrial

Operating Temperature

-40 to +85

TBIAS

Temperature

Under Bias

-55 to +125

TSTG

Storage

Temperature

-55 to +125

Power Dissipation

2.0

IOUT

DC Output Current

5304 tbl 06

Symbol

Parameter(1)

Conditions

Max. Unit

CIN

Input Capacitance

VIN = 3dV

CI/O

I/O Capacitance

VOUT = 3dV

5304 t bl 07

100 99 98 97 96 95 94 93 92 91 90

87 86 85 84 83 82 81

89 88

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

VDDQ

VSS

I/OP2

I/O15

I/O14

VSS

VDDQ

I/O13

I/O12

VSS

VDD

I/O11

I/O10

VDDQ

VSS

I/O9

I/O8

VSS

VDDQ

VSS

I/OP1

I/O7

I/O6

VSS

VDDQ

I/O5

I/O4

VSS

VDD

I/O3

I/O2

VDDQ

VSS

I/O1

I/O0

VSS

VDDQ

5304 drw 02a

VDD(1)

A10

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to V

as long as

the input voltage is ≥ VIH.

2. Pin 84 is reserved for a future 16M.

3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective

JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows

these pins to be left unconnected, tied LOW (V SS), or tied HIGH (V DD).

Symbol

Parameter(1)

Conditions

Max. Unit

CIN

Input Capacitance

VIN = 3dV

CI/O

I/O Capacitance

VOUT = 3dV

5304 tbl 07a

100 TQFP Capacitance(1)

(TA = +25° C, f = 1.0MHz)

Symbol

Parameter(1)

Conditions

Max. Unit

CIN

Input Capacitance

VIN = 3dV

TBD

CI/O

I/O Capacitance

VOUT= 3 dV

TBD

5304 t bl0 7b

165 fBGA Capacitance(1)

(TA = +25° C, f = 1.0MHz)

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