ST72325AR7-Auto datasheet(43/243 Pages) STMICROELECTRONICS

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Supply, reset and clock management

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6.3

Phase locked loop

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to

multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option

byte. If the PLL is disabled, then fOSC2 =fOSC/2.

Caution:

The PLL is not recommended for applications where timing accuracy is required (see

Section 19.5.6: PLL characteristics).

Figure 11.

PLL block diagram

6.4

Multi-oscillator (MO)

The main clock of the ST7 can be generated by three different source types coming from the

multi-oscillator block:

●

an external source

●

4 crystal or ceramic resonator oscillators

●

an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is

selectable through the option byte. The associated hardware configurations are shown in

Table 11. Refer to Section 19: Electrical characteristicsfor more details.

External clock source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle

has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/ceramic oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main

clock of the ST7. The selection within a list of four oscillators with different frequency ranges

has to be done by option byte in order to reduce consumption (refer to Section 21.1.1: Flash

configurationfor more details on the frequency ranges). In this mode of the multi-oscillator,

the resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and start-up stabilization time. The loading

capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the

oscillator start-up phase.

PLL OPTION BIT

PLL x 2

fOSC2

/ 2

fOSC

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