ST72325AR7-Auto datasheet(85/243 Pages) STMICROELECTRONICS

Nome de Peças	ST72325AR7-Auto

Descrição Electrónicos	SCI asynchronous serial interface

PDF	243 Pages

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Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

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Obsolete

Product(s)

- Obsolete

Product(s)

ST72325xxx-Auto

Watchdog timer (WDG)

Doc ID 13770 Rev 3

85/243

10.9

10.9.1

Control register (WDGCR)

WDGCR

Reset value: 0111 1111 (7Fh)

543

WDGA

T[6:0]

Table 37.

WDGCR register description

Bit

Name

Function

7WDGA

Activation bit

This bit is set by software and only cleared by hardware after a reset. When

WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

6:0

T[6:0]

7-bit counter (MSB to LSB)

These bits contain the value of the watchdog counter. It is decremented every 16384

fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

Table 38.

Watchdog timer register map and reset values

Address

(Hex.)

label

76543210

002Ah

WDGCR

Reset Value

WDGA

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