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ST7DALIF2 Folha de dados(PDF) 119 Page - STMicroelectronics

Nome de Peças ST7DALIF2
Descrição Electrónicos  Configurable watchdog timer
PDF  171 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7DALIF2 Folha de dados(HTML) 119 Page - STMicroelectronics

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Instruction set
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19
Instruction set
19.1
CPU addressing modes
The CPU features 17 different addressing modes which can be classified in 7 main groups
(see Table 54).
:
The CPU Instruction Set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be divided in two submodes called
long and short:
●
Long addressing mode is more powerful because it can use the full 64 Kbyte address
space, however it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 54.
Addressing mode groups
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset byte,#5
Table 55.
CPU addressing mode overview
Mode
Syntax
Destination
Pointer address
(Hex.)
Pointer size
(Hex.)
Length
(bytes)
Inherent
nop
+ 0
Immediate
ld A,#$55
+ 1
Short
Direct
ld A,$10
00..FF
+ 1
Long
Direct
ld A,$1000
0000..FFFF
+ 2
No offset
Direct
Indexed
ld A,(X)
00..FF
+ 0
Short
Direct
Indexed
ld A,($10,X)
00..1FE
+ 1
Long
Direct
Indexed
ld A,($1000,X)
0000..FFFF
+ 2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+ 2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+ 2
Short
Indirect
Indexed
ld A,([$10],X)
00..1FE
00..FF
byte
+ 2
Long
Indirect
Indexed
ld A,([$10.w],X)
0000..FFFF
00..FF
word
+ 2



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