ST7DALIF2 datasheet(117/171 Pages) STMICROELECTRONICS

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ST7DALIF2

10-bit A/D converter (ADC)

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18.7.2

Data register high (ADCDRH)

Read Only

Reset Value: xxxx xxxx (xxh)

Bits 7:0 = D[9:2] MSB of Analog Converted Value

18.7.3

AMP control/data register low (ADCDRL)

Read/Write

Reset Value: 0000 00xx (0xh)

Bits 7:5 = Reserved. Forced by hardware to 0.

Bit 4 = AMPCAL Amplifier Calibration Bit

This bit is set and cleared by software. User is suggested to use this bit to calibrate the ADC

when amplifier is ON. Setting this bit internally connects amplifier input to 0 V. Hence,

corresponding ADC output can be used in software to eliminate amplifier-offset error.

0: Calibration off

1: Calibration on (The input voltage of the amp is set to 0V)

Note:

It is advised to use this bit to calibrate the ADC when the amplifier is ON. Setting this bit

internally connects the amplifier input to 0v. Hence, the corresponding ADC output can be

used in software to eliminate an amplifier-offset error.

Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used together with the SPEED bit to configure

the ADC clock speed as shown on the table below.

AIN3

AIN4

AIN5

AIN6

The number of channels is device dependent. Refer to Section 4: Pin description on page 13.

Table 51.

Channel selection bits (continued)

Channel pin(1)

CH2

CH1

CH0

AMP CAL

SLOW

AMPSEL

Table 52.

ADC clock speed selection

fADC

SLOW

SPEED

fCPU/2

fCPU

fCPU/4

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