ST7DALIF2 datasheet(70/171 Pages) STMICROELECTRONICS

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Watchdog timer (WDG)

ST7DALIF2

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the watchdog is disabled. The value to be stored in the CR register must be between FFh

and C0h (see Table 34):

●

The WDGA bit is set (watchdog enabled)

●

The T6 bit is set to prevent generating an immediate reset

●

The T[5:0] bits contain the number of increments which represents the time delay

before the watchdog produces a reset.

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by

a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Note:

The timing variation shown in Table 34 is due to the unknown status of the prescaler when

writing to the CR register.

The number of CPU clock cycles applied during the RESET phase (256 or 4096) must be

taken into account in addition to these timings.

13.4

Hardware watchdog option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the

WDGA bit in the CR is not used.

Refer to the Option Byte description in Section 22.1 on page 161.

13.4.1

Using Halt mode with the WDG (WDGHALT option)

If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT

instruction), it is recommended before executing the HALT instruction to refresh the WDG

counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

The same behavior occurs in Active-halt mode.

13.5

Interrupts

None.

Table 34.

Watchdog timing (fCPU = 8 MHz.)

WDG counter code

min

[ms]

max

[ms]

C0h

FFh

127

128

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