SPC56EL70L3 datasheet(76/128 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

76/128

DocID023953 Rev 5

3.4

Decoupling capacitors

The internal voltage regulator requires an external NPN ballast and some additional

decoupling capacitors. These capacitors shall be placed on the board as close as possible

to the associated pin.

VDD_HV_ADV

3.3 V ADC supply voltage

—

3.0

3.63

VSS_HV_AD0

VSS_HV_AD1

ADC_0 ground and low reference voltage

ADC_1 ground and low reference voltage

—0

VSS_HV_ADV

3.3 V ADC supply ground

—

VDD_LV_REGCOR(4)

Internal supply voltage

—

VSS_LV_REGCOR(5)

Internal reference voltage

—

VDD_LV_CORx(2)

Internal supply voltage

—

VSS_LV_CORx(3)

Internal reference voltage

—

VDD_LV_PLL(2)

Internal supply voltage

—

VSS_LV_PLL(3)

Internal reference voltage

—

Ambient temperature under bias

fCPU

 120 MHz

–40

125

°C

Junction temperature under bias

—

–40

150

°C

1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and

I/Os DC electrical specification may not be guaranteed.

2. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage

source.

3. VDD_HV_ADRx must always be applied and should be stable before LBIST starts. If this supply is not above its absolute

minimum level, LBIST operations can fail.

4. Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an

on-chip voltage regulator.

5. For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds

(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.

Table 9. Recommended operating conditions (3.3 V) (continued)

Symbol

Parameter

Conditions

Min(1)

Max

Unit

Table 10. Decoupling capacitors

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

CCOL

External decoupling /

stability capacitor

Accuracy -50%/+35%.

Max ESR = 100 mΩ.

µF

CLV1

External decoupling /

stability capacitor

Sum of CLV1 placed close to

VDD/VSS_LV_CORy pairs(2).

12µF

40µF

µF

CLV2

External decoupling /

stability capacitor

Sum of CLV2 placed close to

VDD/VSS_LV_CORy pairs shall be

between 300 nF and 900 nF.

100(2)

CPMU1

External decoupling /

stability capacitor

Accuracy -50%/+35%.

µF

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