EM357-RTR datasheet(103/241 Pages) SILABS

103 / 241 page

103

Rev 1.3

SC1_DMASTAT: Address: 0x4000C82C Reset: 0x0



SC2_DMASTAT: Address: 0x4000C02C Reset: 0x0



SC1_DMASTAT: Serial DMA Status Register



SC2_DMASTAT: Serial DMA Status Register

Bit

Name

Bit

Name

Bit

Name

SC_RXSSEL

SC_RXFRMB SC_RXFRMA

Bit

Name

SC_RXPARB SC_RXPARA SC_RXOVFB SC_RXOVFA SC_TXACTB SC_TXACTA SC_RXACTB SC_RXACTA

Bitname

Bitfield Access

Description

SC_RXSSEL

[12:10]

Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode) when nSSEL

deasserts. Cleared when a receive buffer is loaded and when the receive DMA is reset.

0: No count was saved because nSSEL did not deassert.

2: Buffer A's count was saved, nSSEL deasserted once.

3: Buffer B's count was saved, nSSEL deasserted once.

6: Buffer A's count was saved, nSSEL deasserted more than once.

7: Buffer B's count was saved, nSSEL deasserted more than once.

1, 4, 5: Reserved.

SC_RXFRMB

[9]

This bit is set when DMA receive buffer B reads a byte with a frame error from the receive

FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1

in UART mode only)

SC_RXFRMA

[8]

This bit is set when DMA receive buffer A reads a byte with a frame error from the receive

FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1

in UART mode only)

SC_RXPARB

[7]

This bit is set when DMA receive buffer B reads a byte with a parity error from the receive

FIFO. It is cleared the next time buffer B is loaded or when the receive DMA is reset. (SC1

in UART mode only)

SC_RXPARA

[6]

This bit is set when DMA receive buffer A reads a byte with a parity error from the receive

FIFO. It is cleared the next time buffer A is loaded or when the receive DMA is reset. (SC1

in UART mode only)

SC_RXOVFB

[5]

This bit is set when DMA receive buffer B was passed an overrun error from the receive

FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the

FIFO filled up. Buffer B was the next buffer to load, and when it drained the FIFO the over-

run error was passed up to the DMA and flagged with this bit. Cleared the next time buffer

B is loaded and when the receive DMA is reset.

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