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STM32F303VC Folha de dados(PDF) 17 Page - STMicroelectronics |
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STM32F303VC Folha de dados(HTML) 17 Page - STMicroelectronics |
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17 / 148 page  DocID023353 Rev 13 17/148 STM32F303xB STM32F303xC Functional overview 54 Note: For more details about the interconnect actions, please refer to the corresponding sections in the reference manual (RM0316). 3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz. GPIO RTCCLK HSE/32 MC0 TIM16 Clock source used as input channel for HSI and LSI calibration CSS CPU (hard fault) COMPx PVD GPIO TIM1, TIM8, TIM15, 16, 17 Timer break GPIO TIMx External trigger, timer break ADCx DAC1 Conversion external trigger DAC1 COMPx Comparator inverting input Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued) Interconnect source Interconnect destination Interconnect action |
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