LP2995M datasheet(6/13 Pages) NSC

6 / 13 page

Block Diagram

20039301

Description

The LP2995 is a linear bus termination regulator designed to

meet the JEDEC requirements of SSTL-2 and SSTL-3. The

LP2995 is capable of sinking and sourcing current at the

output V

TT, regulating the voltage to equal VDDQ / 2. A

buffered reference voltage that also tracks VDDQ/2is

generated on the V

REF pin for providing a global reference to

the DDR-SDRAM and Northbridge Chipset. V

TT is designed

to track the V

REF voltage with a tight tolerance over the

entire current range while preventing shoot through on the

output stage.

Series Stub Termination Logic (SSTL) was created to im-

prove signal integrity of the data transmission across the

memory bus. This termination scheme is essential to prevent

data error from signal reflections while transmitting at high

frequencies encountered with DDR RAM. The most common

form of termination is Class II single parallel termination. This

involves using one Rs series resistor from the chipset to the

memory and one Rt termination resistor. This implementa-

tion can be seen below in Figure 1.

Typical values for R

S and RT are 25 Ohms although these

can be changed to scale the current requirements from the

LP2995. For determination of the current requirements of

DDR-SDRAM termination please refer to the accompanying

application notes.

20039308

FIGURE 1.

LP2995M Folha de dados(PDF) 6 Page - National Semiconductor (TI)