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LP2995 Folha de dados(PDF) 10 Page - National Semiconductor (TI) |
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LP2995 Folha de dados(HTML) 10 Page - National Semiconductor (TI) |
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10 / 13 page ![]() PCB Layout Considerations 1. AVIN and PVIN should be tied together for optimal per- formance. A local bypass capacitor should be placed as close as possible to the PVIN pin. 2. GND should be connected to a ground plane with mul- tiple vias for improved thermal performance. 3. V SENSE should be connected to the VTT termination bus at the point where regulation is required. For mother- board applications an ideal location would be at the center of the termination bus. 4. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference volt- age. 5. V REF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This ca- pacitor should be located as close as possible to the V REF pin. www.national.com 10 |
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