| Os motores de busca de Datasheet de Componentes eletrônicos |
|
ST6280B Folha de dados(PDF) 49 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST6280B Folha de dados(HTML) 49 Page - STMicroelectronics |
|
49 / 78 page ![]() 49/78 ST62T80B/E80B 4.4 U. A. R. T. (Universal Asynchronous Receiver/Transmitter) The UART provides the basic hardware for asyn- chronous serial communication which, combined with an appropriate software routine, gives a serial interface providing communication with common baud rates (up to 38,400 Baud with an 8MHz ex- ternal oscillator) and flexible character formats. Operating in Half-Duplex mode only, the UART uses 11-bit characters comprising 1 start bit, 9 data bits and 1 Stop bit. Parity is supported by software only for transmit and for checking the received par- ity bit (bit 9). Transmitted data is sent directly, while received data is buffered allowing further data characters to be received while the data is being read out of the receive buffer register. Data trans- mit has priority over data being received. The UART is supplied with an MCU internal clock that is also available in WAIT mode of the processor. 4.4.1 PORTS INTERFACING RXD reception line and TXD emission line are sharing the same external pins as two I/O lines. Therefore, UART configuration requires to set these two I/O lines through the relevant ports reg- isters. The I/O line common with RXD line must be defined as input mode (with or without pull-up) while the I/O line common with TXD line must be defined as output mode (Push-pull or open drain). The transmitted data is inverted and can therefore use a single transistor buffering stage. Defined as input, the RXD line can be read at any time as an I/O line during the UART operation. The TXD pin follows I/O port registers value when UARTOE bit is cleared, which means when no serial transmis- sion is in progress. As a consequence, a perma- nent high level has to be written onto the I/O port in order to achieve a proper stop condition on the TXD line when no transmission is active. Figure 25. UART Block Diagram START DETECTOR DATA SHIFT REGISTER D8 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL REGISTER BAUD RATE RECEIVE BUFFER REGISTER PROGRAMMABLE DIVIDER DIN DOUT D9 BAUD RATE x 8 WRITE READ RXD1 TXD1 UARTOE RX and TX INTERRUPTS TXD DR 0 MUX 1 fOSC VR02009 1095 |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |