TDP158 datasheet(11/55 Pages) TI1

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TDP158

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SLLSEX2 – DECEMBER 2016

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(1)

The Typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted

(2)

The Maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted

6.10 Switching Characteristics, TMDS

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

Data rate

250

6000

Mbps

tTPLH

Propagation delay time (low to high)

see Figure 7 2

250

600

tPHL

Propagation delay time (high to low)

Figure 7 2

250

800

tT(DATA)

Transition time (rise and fall time);

measured at 20% and 80%.

SDA_CTL = L, OE = H, All Data

Rates

Note: Data lane control by I2C only:

See Slew Rate Control

Reg0Ah[1:0] = 11 (default)

tT(CLOCK)

Reg0Ah[1:0] = 10

Reg0Ah[1:0] = 01

Reg0Ah[1:0] = 00

110

TERM = H; Reg0Bh[7:6] = 11

125

Reg0Bh[7:6] = 10

155

TERM = L; Reg0Bh[7:6] = 00

185

TERM = NC; Reg0Bh[7:6] = 01

215

tTX_INTRA

Intra-pair output skew

See Figure 6

Default setting for internal intra-pair

skew adjust, TERM = Z;

SDA_CTL/PRE = L; 1.48 Gbps, 2.97

Gbps, 6 Gbps Data Lines, 148 MHz,

297 MHz Clock

tTX_INTER

Inter-pair output skew

See Figure 6

Default setting for internal inter-pair

skew adjust, TERM = Z;

SDA_CTL/PRE = L; 1.48 Gbps, 2.97

Gbps, 6 Gbps Data Lines, 148 MHz,

297 MHz Clock

100

tJITD1(1.4b)

Total output data jitter HDMI1.4b

DR = 2.97 Gbps, SDA_CTL/PRE =

L, A0/EQ1 = H, A1/EQ2 = H ; See

Figure 7 4 at TTP3

0.2

Tbit

tJITD1(2.0)

Total output data jitter HDMI2.0

In Redriver Mode only ISI will be

compensated for.

3.4 Gbps < Rbit ≤ 3.712 Gps

TERM = Z; SDA_CTL/PRE = L; OE

= H

0.4

Tbit

3.712 Gbps < Rbit < 5.94 Gbps

TERM = Z; SDA_CTL/PRE = L; OE

= H

0.0332Rbit

2 +0.2312

Rbit +

0.1998

Tbit

5.94Gbps

≤ Rbit ≤ 6 Gbps

TERM = Z; SDA_CTL/PRE = L; OE

= H

0.6

Tbit

tJITC1(1.4b)

Total output clock jitter

CLK = 25 MHz, 74.25 MHz, 75

MHz,150 MHz, 297 MHz

0.25

Tbit

tJITC1(2.0)

Total output clock jitter

DR = 6 Gbps: CLK = 150 MHz

0.3

Tbit

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