TDP158 datasheet(34/55 Pages) TI1

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TDP158

SLLSEX2 – DECEMBER 2016

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8.5.7 CSR BIT FIELD DEFINITIONS – MISC CONTROL 0Bh (address = 0Bh)

Figure 31. MISC CONTROL 0Bh Field Descriptions

SLEW_CTL_CLK

Reserved

TERM

DDC_DR_SEL

TMDS_CLOCK

_RATIO_STAT

DDC_TRAIN_S

ETDISABLE

R/W

R/W/U

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. MISC CONTROL 0Bh

Bit

Field

Type

Reset

Description

7:6

SLEW_CTL_CLK

R/W

2’b01

See Slew Rate Control

00 – Slowest ~ 215 ps

01 – Mid-Range 1 (Default) ~ 185 ps

10 – Mid-Range 2 ~ 155 ps

11 – Fastest ~ 125 ps

Values are typical

Reserved

1’b0

Reserved

4:3

TERM

R/W

2’b10

Controls termination for HDMI TX. See Transmitter Impedance

Control

00 – 150 to 300

Ω

01 – No termination

10 – Follows TMDS_CLOCK_RATIO_STATUS bit (default).

When = 1 termination value is 75 to 150

Ω:

When = 0 No termination

11 – 75 to 150

Ω:

Note: When TMDS_CLOCK_RATIO_STATUS bit reg0Bh[1] = 1

this register will automatically be set to 11 for 75 to 150

Ω but

can be overwritten using this address

DDC_DR_SEL

R/W

1’b0

Defines the DDC output speed for DDC bridge 0 = 100kbps

(default) 1 = 400kbps

TMDS_CLOCK_RATIO_STATUS

R/W/U

1’b0

This field is updated from snoop of I2C write to slave address

0xA8 offset 0x20 bit 1 that occurred on the

SDA_SRC/SCL_SRC interface. When bit 1 of address 0xA8

offset 0x20 is written to a 1’b1 or read as a 1’b1, then this field

will be set to a 1’b1. When bit 1 of address 0xA8 offset 0x20 is

written to a 1’b0, then this field will be set to a 1’b0. This field is

reset to default value whenever HPD_SNK is de-asserted for

greater than 2ms. The main function of this bit is to automatically

set the proper TX termination when value = 1.

0 – HDMI1.4b (default)

1 – HDMI2.0

Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 this bit will

reflect the value of the DDC snoop.

Note 2. When DDC_TRAIN_SETDISABLE is 1’b1 this bit is set

by I2C and DDC snoop is ignored. If this bit was set to 1 during

snoop prior to the DDC_TRAIN_SETDISABLE being set to 1 it

will be cleared to 0.

DDC_TRAIN_SETDISABLE

R/W

1’b0

This field indicate the DDC training block function status.

0 – DDC training enable (default)

1 – DDC training disable –DDC snoop disabled

Note 1. When DDC_TRAIN_SETDISABLE is 1’b0 the

TMDS_CLOCK_RATIO_STUATU bit will reflect the value of the

DDC snoop.

Note 2. When DDC_TRAIN_SETDISABLE is 1’b1 this bit is set

by I2C and DDC snoop is ignored and thus automatic TERM

control is ignored and must be manually set and

TMDS_CLOCK_RATIO_STATUS bit will be cleared.

Note 3. To go back to snoop and automatic TERM control this

bit has to be cleared and TERM set back to automatic control.

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