ST92185B datasheet(85/178 Pages) STMICROELECTRONICS

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ST92185B - DISPLAY STORAGE RAM INTERFACE

TDSRAM (Cont’d)

7.3.2 Functional Description

The Data Storage RAM Interface (TRI) manages

the data flows between the different sub-units (dis-

play and CPU interface) and the internal RAM. A

specific set of buses (8 bit data TRIDbus, 13 bit

address TRIAbus) is dedicated to these data

flows.

As this TDSRAM interface has to manage TV ori-

ented real time signals (On-Screen-Display):

– Its timing generator uses the same frequency

generator as for the Display (Pixel frequency

multiplier),

– Its controller is hardware synchronized to the ba-

sic horizontal and vertical sync signals got

through the CSYNC Controller,

– Its architecture gives priority to the TV real time

constraints: whenever there is any access con-

tention between the CPU (only in case of direct

CPU access) and one of the hardware units, the

CPU automatically enters a "wait" configuration

until its request is serviced.

7.3.2.1 TV Line Timesharing

During a TV line, to maintain maximum perform-

ance, a continuous cycle is run repetitively. This

cycle is divided in 8 sub-cycles called "slots".

This 8-slot cycle is repeated continuously until the

next TV line-start occurs (horizontal sync pulse de-

tected). When a horizontal sync pulse is detected,

the running slot is completed and the current cycle

is broken.

The following naming convention is used: "CPU"

stands for direct CPU access slot, "DIS" stands for

Display reading slot. Each slot represents a single

byte exchange (read or write) between the TD-

SRAM memory and the other units:

Display Reading (DIS). 1 byte is read from the

TDSRAM and sent to the display unit, the address

being defined by the display address generator.

CPU Access (CPU). 1 byte is exchanged (read or

written) between the TDSRAM and the CPU, the

address being defined by the CPU address bus.

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