GXM datasheet(58/244 Pages) NSC

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Revision 3.1

Processor Programming (Continued)

There are five types of test operations that can be exe-

cuted:

• Flush buffer read

•Fill buffer write

•Cache write

• Cache read

• Cache flush

These operations are described in detail in Table 3-18. To

fill a cache line with data, the fill buffer must be written four

times. Once the fill buffer holds a complete cache line of

data (16 bytes), a cache write operation transfers the data

from the fill buffer to the cache.

To read the contents of a cache line, a cache read opera-

tion transfers the data in the selected cache line to the

flush buffer. Once the flush buffer is loaded, the program-

mer accesses the contents of the flush buffer by executing

four flush buffer read operations.

Table 3-18. Cache Test Operations

Test Operation

Code Sequence

Action Taken

Flush Buffer Read

MOV TR5, 0h

MOV dest,TR3

Set DWORD = 0, control = 00 = flush buffer read.

Flush buffer (31:0) --> dest.

MOV TR5, 4h

MOV dest,TR3

Set DWORD = 1, control = 00 = flush buffer read.

Flush buffer (63:32) --> dest.

MOV TR5, 8h

MOV dest,TR3

Set DWORD = 2, control = 00 = flush buffer read.

Flush buffer (95:64) --> dest.

MOV TR5, Ch

MOV dest,TR3

Set DWORD = 3, control = 00 = flush buffer read.

Flush buffer (127:96) --> dest.

Fill Buffer Write

MOV TR5, 0h

MOV TR3, cache_data

Set DWORD = 0, control = 00 = fill buffer write.

Cache_data --> fill buffer (31:0).

MOV TR5, 4h

MOV TR3, cache_data

Set DWORD = 1, control = 00 = fill buffer write.

Cache_data --> fill buffer (63:32).

MOV TR5, 8h

MOV TR3, cache_data

Set DWORD = 2, control = 00 = fill buffer write.

Cache_data --> fill buffer (95:64).

MOV TR5, Ch

MOV TR3, cache_data

Set DWORD = 3, control = 00 = fill buffer write.

Cache_data --> fill buffer (127:96).

Cache Write

MOV TR4, cache_tag

Cache_tag --> tag address, valid and dirty bits.

MOV TR5, line+set+control=01

Fill buffer (127:0) --> cache line (127:0).

Cache Read

MOV TR5, line+set+control=10

MOV dest, TR4

Cache line (127:0) --> flush buffer (127:0).

Cache line tag address, valid/LRU/dirty bits --> dest.

Cache Flush

MOV TR5, 3h

Control = 11 = cache flush, all cache valid bits = 0.

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