A25GFO080QL datasheet(41/58 Pages) AMICC

41 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Read SFDP Register (5Ah)

The A25LQ080 features a 64-Byte Serial Flash Discoverable

Parameter (SFDP) register that contains information about

devices operational capability such as available commands,

timing and other features.

The SFDP parameters are stored in one or more Parameter

Identification (PID) tables. Currently only one PID table is

specified but more may be added in the future. The Read

SFDP Register instruction is compatible with the JEDEC

SFDP standard (JESD216) established in 2011.

The Read SFDP instruction is initiated by driving Chip Select

( S ) Low and shifting the instruction code “5Ah” followed by a

24-bit address (A23-A0)

(1) into the DIO pin. Eight “dummy”

clocks are also required before the SFDP register contents

are shifted out on the falling edge of the 40

th Serial Clock (C)

with most significant bit (MSB) first as shown in figure 31. For

SFDP register values and descriptions, refer to the following

SFDP Definition table.

Note: 1. A23-A6 = 0; A5-A0 are used to define the starting

byte address for the 64-Byte SFDP Register.

Figure 30. Read SFDP Register Instruction Sequence Diagram

Instruction (5Ah)

High Impedance

810

01 2 3 4 5 6 7

24-Bit Address

28 29 30 31

23 22 21

3 21 0

Data Out 1

Data Out 2

DIO

32 33 34 35 36 37 38 39

65 4

40 41 42 43 44 45 46 47

Dummy Byte

MSB

7 6 54 32 1

MSB

7 6 54 32 1

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