UCD3138128APFCR datasheet(45/83 Pages) TI1

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UCD3138128A

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SLUSC99 – JULY 2016

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The crystal circuit biasing should be optimized depending on the total Cload on the crystal. Refer to Table 5 for

recommended bias settings based on Cload.

Table 5. Recommended Bias Settings

Cload

BIAS_R SETTING

0~4pF

5~7pF

8~11pF

12~15pF

16~20pF

9.3.10 Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138xA. They are the 24-bit

timer, 16-bit timer and the watchdog timer

9.3.10.1 24-Bit Timer

There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between two

events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit pre-scalar to

provide longer intervals. The timer has two compare registers (Data Registers). Both can be used to generate an

interrupt after a time interval. . Additionally, the timer has a shadow register (Data Buffer register) which can be

used to store CPU updates of the compare events while still using the timer. The selected shadow register

update mode happens after the compare event matches.

The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be set

either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is stored in the

corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which are the counter

rollover event (overflow), capture events 0 and 1, and the two comparison match events. Each interrupt can be

disabled or enabled.

9.3.10.2 16-Bit PWM Timers

There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a

8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for

generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register)

which can be used to store CPU updates of compare events while still using the timer. The selected shadow

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software

controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by

the two comparison match events. Each comparison match and the overflow interrupts can be disabled or

enabled.

Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output.

The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the

value of the input at the pin.

9.3.10.3 Watchdog Timer

A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off

of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM

processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine.

On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by

firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided

for status monitoring of the watchdog.

9.3.11 General Purpose ADC12

The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:

•

Typical conversion speed of 539 ksps

•

Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence

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