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UCD3138064RGZR Folha de dados(PDF) 18 Page - Texas Instruments |
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UCD3138064RGZR Folha de dados(HTML) 18 Page - Texas Instruments |
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18 / 91 page ![]() 0.00 1.00 2.00 3.00 4.00 5.00 6.00 DPWM ADC12 Front-end Control Peak Current Mode Timer Filter Constant Power/Constant Current SCI GIO Module C001 UCD3138064 SLUSB72B – MARCH 2013 – REVISED SEPTEMBER 2014 www.ti.com 5.9 Typical Clock Gating Power Savings Figure 5-4. Clock Gating Power Savings The power disable control register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more. By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved. 18 Specifications Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: UCD3138064 |
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