UCD3138RMHT datasheet(27/78 Pages) TI1

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Error ADC

(Front End)

Filter

Digital

PWM

EAP

EAN

DPWMA

DPWMB

UCD3138

www.ti.com

SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013

Table 4-1. Interrupt Priority Table (continued)

MODULE COMPONENT OR

NAME

DESCRIPTION

PRIORITY

DPWM3

Same as DPWM1

DPWM2

Same as DPWM1

1) Every (1-256) switching cycles

DPWM1

2) Fault Detection

3) Mode switching

DPWM0

Same as DPWM1

EXT_FAULT_INT

External Faults

Fault pin interrupt

SYS_SSI_INT

System Software

System software interrupt

31 (highest)

4.4

Peripherals

4.4.1

Digital Power Peripherals

At the core of the UCD3138 controller are 3 Digital Power Peripherals (DPP). Each DPP can be

configured to drive from one to eight DPWM outputs. Each DPP consists of:

•

Differential input error ADC (EADC) with sophisticated controls

•

Hardware accelerated digital 2-pole/2-zero PID based compensator

•

Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are

capable of supporting functions like input voltage feed forward, current mode control, and constant

current/constant power, etc.. The simplest configuration is shown in the following figure:

4.4.1.1

Front End

Figure 4-1 shows the block diagram of the front end module. It consists of a differential amplifier, an

adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging

filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert

with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range

with 6 bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended

result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output

could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE

value such that the minimum resolution is maintained that still allows the voltage to fit within the range of

the measurement. The EADC control logic receives the sample request from the DPWM module for

initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the

digital compensator for processing of the representative error. The set point DAC has 10 bits with an

additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a

variety of sources to facilitate things like soft start, nested loops, etc. Some additional features include the

ability to change the polarity of the error measurement and an absolute value mode which automatically

adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration; front-end 2 is

recommended for implementing peak current mode control. In this mode topologies like the phase shifted

full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be

ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This

eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is

a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified

in the Electrical Characteristics table.

Functional Overview

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