AT89C5131-RDTIL datasheet(154/176 Pages) ATMEL

154 / 176 page

154

AT89C5131

4136B–USB–09/03

Notes:

1. Operating I

CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 73.), VIL =

SS + 0.5V,

VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure

70.).

2. Idle I

CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -

0.5V; XTAL2 N.C; Port 0 = V

CC; EA = RST = VSS (see Figure 71).

3. Power-down I

CC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-

ure 72.). In addition, the WDT must be inactive and the POF flag must be set.

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V

OLS of ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed

0.45V with maxi V

OL peak 0.6V. A Schmitt Trigger use is not necessary.

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.

6. Under steady state (non-transient) conditions, I

OL must be externally limited as follows:

Maximum I

OL per port pin: 10 mA

Maximum I

OL per 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I

OL for all output pins: 71 mA

If I

OL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

Figure 70. I

CC Test Condition, Active Mode

PFDM

Power Fail Low Level Threshold

2.2

Power fail hysteresis V

PFDP - VPFDM

0.15

Symbol

Parameter

Min

Typ

(5)

Max

Unit

Test Conditions

VCC

(NC)

CLOCK

SIGNAL

All other pins are disconnected.

RST

XTAL2

XTAL1

VSS

VCC

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