AT89C5131-RDTIL datasheet(120/176 Pages) ATMEL

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AT89C5131

4136B–USB–09/03

•

Endpoint FIFO reset

Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer

to its original value, resets the byte counter of the endpoint (UBYCTLX and

UBYCTHX registers), and resets the data toggle bit (DTGL bit in UEPCONX).

The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the

corresponding bit in the UEPRST register.

For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then

0000 0000b in the UEPRST register.

Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.

Read/Write Data FIFO

Read Data FIFO

The read access for each OUT endpoint is performed using the UEPDATX register.

After a new valid packet has been received on an Endpoint, the data are stored into the

FIFO and the byte counter of the endpoint is updated (UBYCTLX and UBYCTHX regis-

ters). The firmware has to store the endpoint byte counter before any access to the

endpoint FIFO. The byte counter is not updated when reading the FIFO.

To read data from an endpoint, select the correct endpoint number in UEPNUM and

read the UEPDATX register. This action automatically decreases the corresponding

address vector, and the next data is then available in the UEPDATX register.

Write Data FIFO

The write access for each IN endpoint is performed using the UEPDATX register.

To write a byte into an IN endpoint FIFO, select the correct endpoint number in UEP-

NUM and write into the UEPDATX register. The corresponding address vector is

automatically increased, and another write can be carried out.

Warning 1: The byte counter is not updated.

Warning 2: Do not write more bytes than supported by the corresponding endpoint.

FIFO Mapping

Figure 58. Endpoint FIFO Configuration

UEPNUM

Endpoint 0

Endpoint 6

UEPSTA0

UEPCON0

UEPDAT0

UEPSTA6

UEPCON6

UEPDAT6

SFR registers

UEPSTAX

UEPCONX

UEPDATX

UBYCTH0

UBYCTL0

UBYCTH6

UBYCTL6

UBYCTHX

UBYCTLX

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