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AT89C5131-RDTIL Folha de dados(PDF) 111 Page - ATMEL Corporation |
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AT89C5131-RDTIL Folha de dados(HTML) 111 Page - ATMEL Corporation |
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111 / 176 page ![]() 111 AT89C5131 4136B–USB–09/03 Figure 52. Format and State in the Slave Transmitter Mode Table 83. Status for Miscellaneous States SSLA R A Data A Data P or S A A8h B8h C0h P or S A C8h All 1’s A B0h Data A n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number (contained in SSCS) corresponds to a defined state of the TWI bus Reception of the own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (AA=0) Status Code (SSCS) Status of the TWI bus and TWI hardware Application Software Response Next action taken by TWI software To/From SSDAT To SSCON S T A S T O S I A A F8h No relevant state information available; SI= 0 No SSDAT action No SSCON action Wait or proceed current transfer 00h Bus error due to an illegal START or STOP condition No SSDAT action 0 1 0 X Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and STO is reset |
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