SP6655 datasheet(14/16 Pages) SIPEX

14 / 16 page

Date: 7/12/04

SP6655 High Efficiency 400mA Synchronous Buck Regulator

APPLICATION INFORMATION

SP6655 Component Sample Layout

SP6655 PC Layout Top Side

SP6655 PC Layout Bottom Side

rules should be followed. Refer to the typical

application schematic on page 1 and the sample

PCB layout shown in the following figures to

illustrate how to layout a SP6655 power supply.

Avoid injecting noise into the sensitive part of

circuit via the ground plane. Input and output

capacitors conduct high frequency current through

the ground plane. Separate the control and power

grounds and connect them together at a single

point. Power ground plane is shown in the figure

titled PCB top sample layout and connects the

ground of the COUT capacitor to the ground of the

CIN capacitor and then to the PGND pin 10. The

control ground plane connects from pin 9 GND to

ground of the CVIN capacitor and the RI ground

return of the feedback resistor. These two separate

control and power ground planes come together in

the figure titled PCB top sample layout where

SP6655 pin 9 GND is connected to pin 10 PGND.

Power loops on the input and output of the con-

verter should be laid out with the shortest and

widest traces possible. The longer and narrower

the trace, the higher the resistance and inductance

it will have. The length of traces in series with the

capacitors increases its ESR and ESL and reduces

their effectiveness at high frequencies. Therefore,

put the 1

µF bypass capacitor as close to the VINand

GND pins of the converter as possible, the 10

µF

CIN close to the PVIN pin and the 10µF output

capacitor as close to the inductor as possible. The

external voltage feedback network RF, RI and

feedforward capacitor CF should be placed very

close to the FB pin. Any noise traces like the LX

pin should be kept away from the voltage feedback

network and separated from it by using power

ground copper to minimize EMI.

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